Technical Field
The invention generally relates to solid-state drive storage devices, and in particular to devices comprising phase change memory integrated circuits and methods of writing to and/or reading data from such devices.
Description of the Related Art
Phase Change Memory (“PCM”) is a frontrunner technology for the next generation of Solid-State Drive (“SSD”) based storage and extended memory subsystems. A main drawback of PCM memories is the asymmetric read/write latencies: the write time for storing a block of information is much longer, compared to the time required for accessing the same amount of data during a read operation. When high-speed interfaces are used, as in DRAM, this time difference is greater than an order of magnitude. As a result of this performance difference, future Solid-state-Drives (“SSDs”) that would be based on PCM could yield very low write performance (compared to the read performance) and high variability on mixed workloads. The most common approach to this problem is to use a DRAM-based cache in the SSD in order to coalesce write commands, and reduce effective latency. However, this approach is not optimal, as the cache is limited in size: its effect depends on the ratio of the DRAM size to the total PCM memory space.
In general, SSDs involve multiple channels that operate in parallel. Each channel consists of a number of independently accessed Integrated Circuits (“ICs”), which share the same data bus. A data block is defined as an entity that can be written at once; thus, its size depends on the number of concurrent write operations implemented in the PCM IC. Due to the limited size, in terms of bytes, of a data block supported by a PCM IC, programming of a single page (a page consists of a number of such data blocks) requires multiple program cycles, which results in a higher write time.
One solution to this problem is to increase the number of concurrent write operations per PCM IC, in order to increase the data block size and thus to decrease the number of program cycles. There are some limitations on the maximum number of write concurrent write operations that can be integrated in a chip due to the layout technology used and the benefits of this type of solution diminish as the page size increases, a common trend in today's storage systems. Another approach is to split the page to multiple channels and store the segments to independent channels, but such an approach does not address the problem of the performance difference between read and write.